1. Technical Field
The embodiments described herein relate to a test apparatus, and more particularly, to an apparatus and a method for testing setup/hold time.
2. Related Art
One important parameters during writing operations of a semiconductor integrated circuit, and more particularly of a semiconductor memory device, is setup/hold time. Here, only when the setup/hold time have proper margins can data to be written become centered according to a data strobe signal ‘DQSB’. As a result, the data can be accurately written in a memory region of the semiconductor integrated circuit.
FIG. 1 is a schematic block diagram of a conventional data input apparatus of a semiconductor integrated circuit. In FIG. 1, a data input apparatus 1 includes a plurality of data input units DIP_DQ0 to DIP_DQ7 and an off-chip driver calibration unit 10. All of the plurality of data input units DIP_DQ0 to DIP_DQ7 are structured to be the same.
Each of the plurality of data input units DIP_DQ0 to DIP_DQ7 are structured to receive an enable signal ‘ENDINB’, data signals ‘DATA<0:7>’, and a data strobe signal ‘DQSB’ as inputs. Here, the plurality of data input units DIP_DQ0 to DIP_DQ7 are connected in a one-to-one correspondence with data pins DQ0 to DQ7 (not shown).
The off chip driver calibration unit 10 is structured to calibrate a level of output data of an off-chip driver (not shown). Here, the off-chip driver calibration unit 10 receives data previously obtained, i.e., pre-fetched, in one of the plurality of data input units DIP_DQ0 to DIP_DQ7, and receives a data clock signal ‘DCLK’ as inputs to output the off chip driver calibration signals ‘PU_INCD’, ‘PU_DECD’, ‘PD_INCD’, and ‘PD_DECD’. The off chip driver calibration signals ‘PU_INCD’, ‘PU_DECD’, ‘PD_INCD’, and ‘PD_DECD’ are used to calibrate the level of output data of the off-chip driver (not shown).
FIG. 2 is a schematic block diagram of a conventional data input unit DIP_DQ6 used in the apparatus of FIG. In FIG. 2, the data input unit DIP_DQ6 includes an input buffer 21, a pre-fetch circuit unit 22, and a write driver 23. The off-chip driver calibration unit 10 receives output data of the pre-fetch circuit unit 22 as input.
The input buffer 21 buffers and outputs data signal ‘DATA<6>’ when an enable signal ‘ENDINB’ is enabled. The pre-fetch circuit unit 22 will pre-fetch output data, i.e., pre-fetch 4 bits, of the input buffer 21 to center the output data according to the data strobe signal ‘DQSB’, and then output the output data. The write driver 23 drives output data of the pre-fetch circuit unit 22 to write the output data in a memory region of the semiconductor integrated circuit.
FIG. 3 is a schematic block diagram of a conventional off-chip driver calibration unit used in the apparatus of FIG. 1. In FIG. 3, the off-chip driver calibration unit 10 includes a latch circuit unit 11 and a decoder 12.
The latch circuit unit 11 latches data signals ‘ALGNR0B’, ‘ALGNF0B’, ‘ALGNR1B’, and ‘ALGNF1B’ output from the pre-fetch circuit unit 22 according to the data clock signal ‘DCLK’ to output latched data signals ‘DIN0B’, ‘DIN1B’, ‘DIN2B’, and ‘DIN3B’. The decoder 12 decodes the latched data signals ‘DIN0B’, ‘DIN1B’, ‘DIN2B’, and ‘DIN3B’ to output the off-chip driver calibration signals ‘PU_INCD’, ‘PU_DECD’, ‘PD_INCD’, and ‘PD_DECD’.
Considering circuit arrangements inside a chip of a semiconductor integrated circuit, simulation operations, i.e., setup/hold simulations, for setting a setup/hold margin in a data writing operation to a proper level is performed by a modeling operation in consideration of signal loads.
However, the data input apparatus 1 (in FIG. 1) is problematic. For example, the circuit configurations of the data input apparatus 1 (in FIG. 1) are not capable of performing a test for judging appropriateness of setup/hold time selectively with respect to a plurality of data pins. Although data pins of a semiconductor integrated circuit are in the one-to-one correspondence with the plurality of data input units DIP_DQ0 to DIP_DQ7, the plurality of data input units DIP_DQ0 to DIP_DQ7 have different data output characteristics from each other due to differences during fabrication processes and operation circumstances.
In addition, since the data input apparatus 1 (in FIG. 1) is not capable of testing respective data pins separately, one of the margins of setup/hold time in the designed circuit according to the setup/hold simulation will not be sufficient. Accordingly, since data to be written in the memory region are not centered when margins of setup/hold time are insufficient, a revision operation is required, thereby causing a loss production time and increasing production costs. Moreover, when performing the revision operation, since another simulation for data alignment should be performed, as well as the setup/hold simulation, additional time and cost are needed due to additional simulations.